In recent years, a substrate which has a semiconductor layer on an insulating layer has received attention. This substrate is referred to as a Semiconductor-On-Insulator substrate or Silicon-On-Insulator substrate. The latter substrate is one of Semiconductor-On-Insulator substrates and has a semiconductor layer made of silicon. Both Semiconductor-On-Insulator substrates and Silicon-On-Insulator substrates are called SOI substrates.
As an SOI substrate, a substrate which has an insulating layer not in the entire region but in a partial region under a semiconductor layer or an Si layer has been proposed. A related art is disclosed in Japanese Patent No. 2794702 (semiconductor device manufacturing method). A manufacturing method disclosed in Japanese Patent No. 2794702 forms an n+-layer on an n−-silicon substrate serving as the first substrate, forms a thermal oxide film (SiO2) on the n+-layer, and then removes an unnecessary portion of the thermal oxide film. With this operation, the thermal oxide film is partially left on the n+-layer. After that, an epitaxial layer is grown on an exposed portion of the n+-layer. At this time, a polysilicon layer is formed on the partial thermal oxide film. The main surface of the first substrate is polished such that the epitaxial and polysilicon layers have the same height. Then, the main surface side of the first substrate is bonded to the second substrate, thereby obtaining a final substrate. This final substrate has a partial buried insulating layer (thermal oxide film) under a portion constituted by the first substrate. A semiconductor device is formed on the portion constituted by the first substrate.
In the manufacturing method disclosed in Japanese Patent No. 2794702, a portion on which a device is to be formed is the first substrate itself in a final substrate to be manufactured, and the thickness is very large. For this reason, it is difficult for the final substrate to enjoy the advantages of a general SOI substrate. More specifically, a substrate obtained by the manufacturing method disclosed in Japanese Patent No. 2794702 cannot sufficiently exhibit the advantages of an SOI substrate, such as low power consumption, high-speed operation, and the like.
The manufacturing method disclosed in Japanese Patent No. 2794702 polishes the first substrate, in which the epitaxial layer and polysilicon layer are combined on the surface, before bonding the first and second substrates. However, there is a limit to planarization of the surface of the first substrate by the polishing step. More specifically, if the polishing conditions are set for the epitaxial layer, the planarity of the polysilicon layer becomes poor. On the other hand, if the polishing conditions are set for the polysilicon layer, the planarity of the epitaxial layer becomes poor. Additionally, a level difference may occur between the epitaxial layer and the polysilicon layer.
If the first substrate in which the epitaxial layer and polysilicon layer are combined on the surface has poor surface planarity, poor bonding is likely to occur in bonding the first substrate to the second substrate. This poor bonding interferes with the formation of a high-quality device.